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VLSI stands for very large scale integration, VLSI physical design automation deals with the study of algorithms associated with the physical design process.

The [course_title] is specifically intended for individuals to learn the basic design flow in VLSI physical design automation. Following that, you will learn the essential data structures and algorithms in an efficient manner. This course will set you up with some examples and assignments to grasp the concepts involved as well as recognise the challenges associated with it.

Assessment

This course does not involve any written exams. Students need to answer 5 assignment questions to complete the course, the answers will be in the form of written work in pdf or word. Students can write the answers in their own time. Each answer needs to be 200 words (1 Page). Once the answers are submitted, the tutor will check and assess the work.

Certification

Edukite courses are free to study. To successfully complete a course you must submit all the assignment of the course as part of the assessment. Upon successful completion of a course, you can choose to make your achievement formal by obtaining your Certificate at a cost of £49.

Having an Official Edukite Certification is a great way to celebrate and share your success. You can:

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Course Credit: NPTEL

Course Curriculum

Algorithmic Level Techniques for Low Power Design 00:31:00
Boundary Scan Standard 00:28:00
Built-in Self-Test (Part 1) 00:31:00
Built-in Self-Test (Part 2) 00:23:00
Clock Design (Part 1) 00:45:00
Clock Design (Part 2) 00:29:00
Clock Design (Part 3) 00:29:00
CLOCK NETWORK SYNTHESIS (PART 1) 00:33:00
CLOCK NETWORK SYNTHESIS (PART 2) 00:31:00
CLOCK NETWORK SYNTHESIS (PART 3) 00:34:00
CLOCK NETWORK SYNTHESIS (PART 4) 00:35:00
Design for Testability 00:30:00
Design Representation 00:32:00
Design Rule Check 00:29:00
Detailed Routing (Part 1) 00:31:00
Detailed Routing (Part 2) 00:29:00
Detailed Routing (Part 3) 00:33:00
Detailed Routing (Part 4) 00:30:00
Fault Modeling (Part 1) 00:34:00
Fault Simulation (Part 1) 00:29:00
Fault Simulation (Part 2) 00:34:00
Floor planning 00:30:00
Floor planning Algorithms 00:30:00
Gate Level Design for Low Power (Part 1) 00:29:00
Gate Level Design for Low Power (Part 2) 00:31:00
Global Routing (Part 1) 00:36:00
Global Routing (Part 2) 00:30:00
Grid Routing (Part 1) 00:30:00
Grid Routing (Part 2) 00:29:00
Grid Routing (Part 3) 00:38:00
Interconnect Modeling (Part 1) 00:33:00
Interconnect Modeling (Part 2) 00:32:00
Introduction 0003 00:31:00
Layout Compaction (Part 1) 00:25:00
Layout Compaction (Part 2) 00:34:00
Low Power VLSI Design 00:32:00
Miscellaneous Approaches to Timing Optimization 00:32:00
mod09lec50 00:29:00
Other Low Power Design Techniques 00:25:00
Partitioning 00:34:00
Performance-Driven Design Flow 00:23:00
Physical Synthesis (Part 1) 00:29:00
Physical Synthesis (Part 2) 00:31:00
Pin Assignment 00:24:00
Placement (Part 1) 00:34:00
Placement (Part 2) 00:34:00
Placement (Part 3) 00:30:00
Placement (Part 4) 00:31:00
POWER AND GROUND ROUTING 00:27:00
Summarization of the Course 00:15:00
Techniques to Reduce Power 00:36:00
Test Pattern Generation 00:33:00
Testing of VLSI Circuits 00:30:00
Time Closure (Part 1) 00:35:00
Time Closure (Part 2) 00:35:00
Time Closure (Part 3) 00:31:00
Time Closure (Part 4) 00:30:00
Time Closure (Part 5) 00:33:00
Timing Driven Placement 00:29:00
Timing Driven Routing 00:33:00
VLSI Design Styles (Part 1) 00:36:00
VLSI Design Styles (Part 2) 00:30:00
VLSI Physical Design Automation (Part 1) 00:30:00
VLSI Physical Design Automation (Part 2) 00:29:00
Assessment
Submit Your Assignment 00:00:00
Certification 00:00:00

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