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This course offers an introduction to the engineering of digital systems. Starting with MOS transistors, it develops building blocks, combinational and sequential circuits. Both hardware and software mechanisms are explored through a series of design examples. Lab exercises are intended to give students “hands-on” experience in designing digital systems, each student completes a gate-level design for a reduced instruction set computer (RISC) processor during the course.
Assessment
This course does not involve any written exams. Students need to answer 5 assignment questions to complete the course, the answers will be in the form of written work in pdf or word. Students can write the answers in their own time. Each answer needs to be 200 words (1 Page). Once the answers are submitted, the tutor will check and assess the work.
Certification
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Course Credit: MIT
Course Curriculum
| Module 01 | |||
| Course overview and mechanics, basics of information | 00:05:00 | ||
| Digital abstraction, combinational logic, voltage-based encoding | 00:05:00 | ||
| CMOS technology, gate design, timing | 00:05:00 | ||
| Canonical forms; synthesis, simplification | 00:05:00 | ||
| Sequential logic | 00:10:00 | ||
| Storage elements, finite state machines | 00:10:00 | ||
| Synchronization, metastability | 00:05:00 | ||
| Pipelining; throughput and latency | 00:05:00 | ||
| Case study: multipliers | 00:10:00 | ||
| Beta instruction set architecture, compilation | 00:10:00 | ||
| Machine language programming issues | 00:05:00 | ||
| Models of computation, programmable architectures | 00:10:00 | ||
| Module 02 | |||
| Stacks and procedures | 00:05:00 | ||
| Multilevel memories; locality, performance, caches | 00:05:00 | ||
| Cache design issues | 00:05:00 | ||
| Virtual memory: mapping, protection, contexts | 00:10:00 | ||
| Virtual machines: time sharing, OS kernels, supervisor calls | 00:05:00 | ||
| Non-pipelined Beta implementation | 00:10:00 | ||
| Devices and interrupt handlers, preemptive interrupts, real-time issues | 00:05:00 | ||
| Communication issues: busses, networks, protocols | 00:05:00 | ||
| Communicating processes: semaphores, synchronization, atomicity, deadlock | 00:10:00 | ||
| Pipelined Beta implementation, bypassing | 00:05:00 | ||
| Pipeline issues: delay slots, annulment, exceptions | 00:10:00 | ||
| Parallel processing, shared memory, cache coherence, consistency criteria | 00:05:00 | ||
| Wrapup lecture | 00:05:00 | ||
| Assessment | |||
| Submit Your Assignment | 00:00:00 | ||
| Certification | 00:00:00 | ||
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