It is a course which takes you on a journey to FPGA based system design technology. It is a science that induces pattern shift in computing.
You will learn how computing have evolved from pure hardware based computing to completely software-based computing. This means that computing system has shrunk down from monolithic sizes to smaller size. It will introduce you to new issues which as a scientist you must embrace as new challenges.
Assessment
This course does not involve any written exams. Students need to answer 5 assignment questions to complete the course, the answers will be in the form of written work in pdf or word. Students can write the answers in their own time. Each answer needs to be 200 words (1 Page). Once the answers are submitted, the tutor will check and assess the work.
Certification
Edukite courses are free to study. To successfully complete a course you must submit all the assignment of the course as part of the assessment. Upon successful completion of a course, you can choose to make your achievement formal by obtaining your Certificate at a cost of £49.
Having an Official Edukite Certification is a great way to celebrate and share your success. You can:
- Add the certificate to your CV or resume and brighten up your career
- Show it to prove your success
Course Credit: Politecnico di Milano
Course Curriculum
| Module 01 | |||
| FPGA computing systems – Course Introduction | 00:03:00 | ||
| FPGA – Reconfiguration in Everyday Life | 00:03:00 | ||
| FPGA – The Needs for Adaptation an overview | 00:05:00 | ||
| FPGA and reconfiguration a 1st definition | 00:05:00 | ||
| FPGA – Runtime management | 00:03:00 | ||
| FPGA – Programmable System on Chip | 00:04:00 | ||
| FPGA – Programmable System on Multiple Chip | 00:07:00 | ||
| FPGA – Reconfigurable Computing a 1st definition | 00:02:00 | ||
| FPGA – Reconfigurable Computing HW vs SW | 00:03:00 | ||
| FPGA – On how to improve the Reconfigurable computing performance via CAD improvements | 00:04:00 | ||
| Module 02 | |||
| FPGA – FPGA Based Reconfigurable Computing | 00:04:00 | ||
| FPGA – System design space exploration and rationale behind partial reconfiguration | 00:15:00 | ||
| FPGA – Getting Familiar with FPGAs | 00:03:00 | ||
| FPGA – Basic Block CLBs and IOBs | 00:06:00 | ||
| FPGA – Basic Block Interconnections | 00:06:00 | ||
| FPGA – Configuration an overview | 00:03:00 | ||
| FPGA – More Details on How To Configure and FPGA the bitstream files | 00:05:00 | ||
| FPGA – Bitstream Composition | 00:04:00 | ||
| FPGA – Configuration Registers | 00:06:00 | ||
| FPGA – How to handle the complexity of an FPGA based system | 00:05:00 | ||
| Module 03 | |||
| FPGA – 4 inputs 1 output OR LUT configuration example | 00:10:00 | ||
| FPGA – From the LUT to the CLB configuration example | 00:08:00 | ||
| FPGA – A simplified FPGA and its configuration settings | 00:05:00 | ||
| FPGA – An Example on how to implement a circuit on a simplified FPGA | 00:09:00 | ||
| FPGA – An Example on how to implement a circuit on a simplified FPGA bitstram generation phase | 00:05:00 | ||
| FPGA – An Example on how to implement a circuit on a simplified FPGA bitstram generation phase SB | 00:04:00 | ||
| FPGA – A Common Vocabulary | 00:05:00 | ||
| FPGA – The 5 W’s | 00:06:00 | ||
| FPGA – Reconfigurable Computing as an Exstension of HWSW Codesing | 00:06:00 | ||
| FPGA – A Classification of SoC Reconfigurations | 00:09:00 | ||
| Module 04 | |||
| FPGA – A Classification of SoMC Reconfigurations | 00:10:00 | ||
| FPGA – Scenarios where Partial Reconfiguration can be effective | 00:07:00 | ||
| FPGA – How to use FPGA Reconfiguration to face area issues | 00:05:00 | ||
| FPGA – How to deal with the Reconfiguration runtime overhead | 00:04:00 | ||
| FPGA – Recurring modules to reuse them to reduce the Reconfiguration time | 00:04:00 | ||
| FPGA – Partial Reconfiguration to reduce the Reconfiguration runtime overhead | 00:06:00 | ||
| FPGA – Runtime management to explore alternative implementations | 00:06:00 | ||
| FPGA – Bitstreams relocation | 00:07:00 | ||
| FPGA – Bitstreams relocation and virtual homogeneity | 00:03:00 | ||
| FPGA – Xilnx Design Flows through years | 00:06:00 | ||
| Module 05 | |||
| FPGA – Partial Reconfiguration Design Flows | 00:05:00 | ||
| FPGA – Xilinx Difference Based Partial Reconfiguration | 00:06:00 | ||
| FPGA – Xilinx Module Based Partial Reconfiguration | 00:05:00 | ||
| FPGA – Xilinx Partial Reconfiguration PR Flow | 00:06:00 | ||
| FPGA – Moudle Based vs Partial Reconfiguration Design Flows | 00:17:00 | ||
| FPGA – Rationale behind DRESD and the work done by the Politecnico di Milano | 00:03:00 | ||
| FPGA – From DRESD to CHANGE and ASAP, two new research initiatives from the Politecnico di Milano | 00:05:00 | ||
| FPGA – CAOS from embedded to heterogeneous distributed FPGA based computing systems | 00:03:00 | ||
| FPGA – Towards distributed FPGA based systems | 00:05:00 | ||
| Assessment | |||
| Submit Your Assignment | 00:00:00 | ||
| Certification | 00:00:00 | ||
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