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This course is offered to graduate and is a project-oriented course to teach new methodologies for designing multi-million-gate CMOS VLSI chips using high-level synthesis tools in conjunction with standard commercial EDA tools. The course focus on modular and robust designs, reusable modules, correctness by construction, architectural exploration, and meeting the area. It also covers timing, and power constraints within the standard cell and FPGA frameworks.


This course does not involve any written exams. Students need to answer 5 assignment questions to complete the course, the answers will be in the form of written work in pdf or word. Students can write the answers in their own time. Each answer need to be 200 words (1 Page). Once the answers are submitted, the tutor will check and assess the work.


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Course Credit: MIT

Course Curriculum

Module 01
Introduction 00:40:00
Digital Design Using Verilog 00:25:00
CMOS Technology and Logic Gates 00:35:00
Verilog Simulation I 00:30:00
Wires 00:35:00
Synthesis 00:30:00
Verilog Simulation II 00:30:00
Clocking 00:30:00
Bluespec I Motivation 00:40:00
Module 02
Bluespec II Designing with Rules 01:00:00
Bluespec III Modules and Interfaces 00:40:00
Bluespec IV Rule Scheduling and Synthesis 00:35:00
Bluespec 00:30:00
Power 00:35:00
Bluespec V Processors 00:30:00
Bluespec VI Modularity and Performance 00:30:00
Transaction Level Design and Verification 00:30:00
Testing 00:30:00
Submit Your Assignment 00:00:00
Certification 00:00:00

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