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What is Computer Architecture? Why do you want to learn Computer Architecture? This is a very interesting course which teaches you how an instruction set architecture is different than implementation or micro-architecture.

You will learn about modern processor design and fundamentals of superscalar processors with a much deeper coverage. This is an advanced course and you are recommended to take a Computer Organization class before attending this class to understand Computer Architecture to fullest sense.

Assessment

This course does not involve any written exams. Students need to answer 5 assignment questions to complete the course, the answers will be in the form of written work in pdf or word. Students can write the answers in their own time. Each answer needs to be 200 words (1 Page). Once the answers are submitted, the tutor will check and assess the work.

Certification

Edukite courses are free to study. To successfully complete a course you must submit all the assignment of the course as part of the assessment. Upon successful completion of a course, you can choose to make your achievement formal by obtaining your Certificate at a cost of £49.

Having an Official Edukite Certification is a great way to celebrate and share your success. You can:

  • Add the certificate to your CV or resume and brighten up your career
  • Show it to prove your success

 

Course Credit: Princeton University

Course Curriculum

Module 01
Computer Architecture – Course Overview 00:05:00
Computer Architecture – Motivation 00:17:00
Computer Architecture – Architecture and Microarchitecture 00:24:00
Computer Architecture – Machine Models 00:16:00
Computer Architecture – Characteristics 00:26:00
Computer Architecture – Microcoded Microarchitecture 00:14:00
Computer Architecture – Pipeline Basics 00:31:00
Computer Architecture – Structural Hazard 00:10:00
Computer Architecture – Data Hazards 00:47:00
Computer Architecture – Control Hazards, Jumps 00:16:00
Computer Architecture – Control Hazards, Branch 00:24:00
Computer Architecture – Control Hazards, Others 00:08:00
Computer Architecture – Memory Technologies 00:23:00
Computer Architecture – Motivation for Caches 00:23:00
Computer Architecture – Classifying Caches 00:28:00
Computer Architecture – Cache Performance 00:17:00
Module 02
Computer Architecture – Superscalar 1 00:07:00
Computer Architecture – Basic Two way In order Superscalar 00:05:00
Computer Architecture – Fetch Logic and Alignment 00:11:00
Computer Architecture – Baseline Superscalar and Alignment 00:04:00
Computer Architecture – Interrupts and Bypassing 00:12:00
Computer Architecture – Interrupts and Exceptions 00:30:00
Computer Architecture – Introduction to Out of Order Processors 00:31:00
Computer Architecture – Review of Out of Order Processors 00:04:00
Module 03
Computer Architecture – I2O2 Processors 00:20:00
Computer Architecture – I2O1 Processors 00:29:00
Computer Architecture – IO3 Processors 00:17:00
Computer Architecture – IO2I Processors 00:05:00
Computer Architecture – Speculation and Branch 00:15:00
Computer Architecture – Register Renaming Introduction 00:11:00
Computer Architecture – Register Renaming with Pointers to IQ and ROB 00:25:00
Computer Architecture – Register Renaming with Values in IQ and ROB 00:12:00
Computer Architecture – Memory Disambiguation 00:10:00
Computer Architecture – Limits of Out of Order Design Complexity 00:13:00
Module 04
Computer Architecture – Introduction to VLIW 00:22:00
Computer Architecture – VLIW Compiler Optimizations 00:22:00
Computer Architecture – Classic VLIW Challenges 00:08:00
Computer Architecture – Introduction to Predication 00:10:00
Computer Architecture – Scheduling Model Review 00:06:00
Computer Architecture – Review of Predication 00:31:00
Computer Architecture – Predication Implementation 00:10:00
Computer Architecture – Speculation Execution 00:26:00
Computer Architecture – Dynamic Events and Clustered VLIWs 00:11:00
Computer Architecture – Case Study IA 64Itanium 00:21:00
Module 05
Computer Architecture – Branch Cost Motivation 00:07:00
Computer Architecture – Branch Prediction Introduction 00:05:00
Computer Architecture – Static Outcome Prediction 00:16:00
Computer Architecture – Dynamic Outcome Prediction 00:29:00
Computer Architecture – Target Address Prediction 00:19:00
Computer Architecture – Basic Cache Optimizations 00:16:00
Computer Architecture – Cache Pipelining 00:14:00
Computer Architecture – Write Buffers 00:10:00
Computer Architecture – Multilevel Caches 00:28:00
Computer Architecture – Victim Caches 00:11:00
Computer Architecture – Prefetching 00:27:00
Computer Architecture – Multiporting and Banking 00:20:00
Module 06
Computer Architecture – Software Memory Optimizations 00:27:00
Computer Architecture – Non blocking Caches 00:20:00
Computer Architecture – Critical Word First and Early Restart 00:03:00
Computer Architecture – Memory Management Introduction 00:13:00
Computer Architecture – Base and Bound Registers 00:12:00
Computer Architecture – Page Based Memory Systems 00:27:00
Computer Architecture – Translation and Protection 00:15:00
Computer Architecture – TLB Processing 00:12:00
Computer Architecture – Address Translation Review 00:10:00
Computer Architecture – Cache and Memory Protection Interaction 00:22:00
Module 07
Computer Architecture – Vector Processor Introduction 00:18:00
Computer Architecture – Vector Parallelism 00:07:00
Computer Architecture – Vector Hardware Optimizations 00:19:00
Computer Architecture – Vector Software and Compiler Optimizations 00:06:00
Computer Architecture – Reduction, ScatterGather, and the Cray 1 00:09:00
Computer Architecture – SIMD 00:07:00
Computer Architecture – Interactive Transcript 00:20:00
Computer Architecture – Multithreading Motivation 00:08:00
Computer Architecture – Coarse Grain Multithreading 00:26:00
Computer Architecture – Simultaneous Multithreading 00:13:00
Computer Architecture – SMT Implementation 00:17:00
Module 08
Computer Architecture – Introduction to Parallelism 00:18:00
Computer Architecture – Sequential Consistency 00:21:00
Computer Architecture – Introduction to Locks 00:04:00
Computer Architecture – Sequential Consistency Review 00:04:00
Computer Architecture – Locks and Semaphores 00:10:00
Computer Architecture – Atomic Operations 00:27:00
Computer Architecture – Memory Fences 00:11:00
Computer Architecture – Dekker’s Algorithm 00:14:00
Computer Architecture – Locking Review 00:02:00
Computer Architecture – Bus Implementation 00:12:00
Computer Architecture – Cache Coherence 00:17:00
Computer Architecture – Bus Based Multiprocessors 00:05:00
Computer Architecture – Cache Coherence Protocols 00:49:00
Computer Architecture – More Cache Coherence Protocols 00:21:00
Module 09
Computer Architecture – Introduction to Interconnection Networks 00:09:00
Computer Architecture – Message Passing 00:27:00
Computer Architecture – Interconnect Design 00:15:00
Computer Architecture – Networking Review 00:08:00
Computer Architecture – Topology 00:19:00
Computer Architecture – Topology Parameters 00:15:00
Computer Architecture – Network Performance 00:16:00
Computer Architecture – Routing and Flow Control 00:21:00
Computer Architecture – Credit Based Flow Control 00:08:00
Computer Architecture – Deadlock 00:10:00
Computer Architecture – False Sharing 00:10:00
Computer Architecture – Introduction to Directory Coherence 00:13:00
Computer Architecture – Implementation 00:29:00
Computer Architecture – Scalability of Directory Coherence 00:14:00
Assessment
Submit Your Assignment 00:00:00
Certification 00:00:00

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